Monday, July 10, 2006
SystemC Activities at DAC
The Open SystemC Initiative (OSCI) invites you to attend the annual SystemC Technology Symposium and North American SystemC Users Group Meeting (NASCUG) co-located at the DAC Conference.
SYSTEMC TECHNOLOGY SYMPOSIUM
Monday, July 24, 2006
11:30am – Registration Opens
12:00 – 1:45pm – Meeting and Panel Discussion
5TH NORTH AMERICAN SYSTEM USERS MEETING (NASCUG)
Monday, July 24, 2005
1:30 pm – Registration
2:00 - 5:00 pm – Meeting
5:00 - 6:00 pm – Beer and Wine Reception
LOCATION
Room 200-210
Moscone Convention Center
San Francisco, CA
REGISTER NOW AS SEATING IS LIMITED!
http://www.nascug.org/5thnascug_registration.htm
SPONSORS
Cadence Design Systems, Inc., Celoxica Ltd., CoWare Inc, ESLX, Forte Design Systems, Inc., Mentor Graphics Corporation, Synopsys, Inc., Doulos Ltd., Jeda Technologies
--------------------------------------------
SYSTEMC SYMPOSIUM HIGHLIGHTS
Detailed agenda is available at http://www.mod-marketing/osci
PANEL: ESL ADOPTION: WINNING STRATEGIES FOR THE ORGANIZATION
Moderated by David Maliniak, EDA editor, Electronic Design
Leading design companies have embraced ESL design and transaction-level modeling (TLM) as the next system-on-chip (SoC) design methodology imperative. With simulation speeds of 1,000x faster than RTL and 10x more productive model development time, ESL and TLM technologies are creating new value by enabling significantly earlier architecture definition and software development for SoC designs, and streamlining hardware implementation and system verification.
But what are the implications for the organization? How are design teams expected to work together to deliver this impact to the bottom line?
Join our panel of experts in this lively discussion on the economic impact of ESL, SystemC, and TLM.
PANELISTS
Terry Doherty, Principal Engineer, Emulex
Ryan Bedwell, System-Level Design Manager, Modem Products Division of the Wireless & Mobile Systems Group, Freescale
Tommi Makelainen, Principal Research Engineer and Program Manager, Computer Architecture Laboratory, Nokia Research Center
Loic Le Toumelin, SOC Methodology Process and Tools, Worldwide Director, Cellular Systems Wireless Division, Texas Instruments
SPECIAL PRESENTATION: EXPLORING SYSTEMC/SYSTEMVERILOG INTERACTION
The IEEE has recently ratified SystemVerilog and SystemC as official IEEE standards respectively known as IEEE Std. 1800™-2005 and IEEE Std. 1666™- 2005. The SystemC and SystemVerilog design and verification languages were developed to deliver exponential increases in design productivity in response to the industry’s perennial challenge – continuing exponential increases in design complexity. These languages are increasingly used in a complementary manner in SOC design. The short overview of these languages and their complementary use will be explored.
PRESENTERS
Johny Srouji, Chair of IEEE SystemVerilog WG
Stuart Swan, Technical Chair of IEEE SystemC WG
REGISTER NOW AS SEATING IS LIMITED!
http://www.thttp://www.nascug.org/5thnascug_registration.htm
--------------------------------------------
NASCUG HIGHLIGHTS
AGENDA: http://www.nascug.org/5th_NASCUG_agenda.html
PRESENTATIONS
Patterns and Issues in SystemC Usage
John Aynsley, Doulos Ltd.
Effective Performance Analysis and Visualization of SystemC Models Adam Donlin, Xilinx Inc.
High-Speed Hardware/Software Co-Verification with CPU Model Generator from Software Code Dai Araki, InterDesign Technologies Inc.
Experience of Migration from eVCs to SystemC Modeling Adesh Sontakke, Texas Instruments
Behavioral SystemC Implementation of an MP3 Decoder Portavales Goldstein, State University of Campinas - UNICAMP
PANEL: EXPLORING THE "FUTURES" OF SYSTEMC Moderated by: Mark McDermott, Adjunct Professor, University of Texas; Vice President, Engineering, Coherent Logix, Inc.
Built upon the cooperative effort of combined vendor technology and user experiences, the IEEE has approved the SystemC language as IEEE Std. 1666. Providing a core for virtually all modeling and verification for system-level design, IEEE 1666 provides the foundation for the next generation of technologies and tools developed around the standard. Help us explore what the future holds for this new standard! As we move to even larger systems, how far can the language go in solving even more complex design challenges?
PANELISTS
Functional Verification: Kota Bhaskar, ElementCXI
Mixed Signal Modeling: Dr. Joanne DeGroat, Associate Professor, Ohio State University
RTOS Modeling: David Black, CTO, ESLX, Inc; Member, OSCI Language Working Group
System Level Design: Mark Burton, Founder, GreenSocs; Chairman, OCP-IP SLD Working Group
DON’T’ MISS THE BEER AND WINE RECEPTION AT 5:00PM!
--------------------------------------------
MORE SYSTEMC AND ESL EVENTS AT DAC!
MONDAY, JULY 24, 9:00am - 5:00 pm | Room: 305 Full Day Tutorial, ESL Design Methodology Using SystemC
http://www2.dac.com/data2/43rd/43AcceptedPapers.nsf/0/144092A4CC618F708725714100710B21
MONDAY, JULY 24, 2:00pm - 5:00 pm | Room: 309 Hands-On Tutorial, Using Virtual System Prototypes to Optimize Architectures for Low Power and Other Key Attributes
http://www2.dac.com/data2/43rd/43acceptedpapers.nsf/0/2745A324433E9B09872571410072BAE8
TUESDAY, JULY 25, 2006, 2:00pm - 4:00pm | Room: 307 Special Session, Bridging the System to RTL Verification Gap
http://www2.dac.com/data2/43rd/43acceptedpapers.nsf/websessions/7
WEDNESDAY, JULY 26, 10:30am - 12:00pm | Room: 306-308 Technical Panel, Building a Standard ESL Design and Verification Methodology: Is It Just a Dream?
http://www2.dac.com/data2/43rd/43acceptedpapers.nsf/websessions/22
WEDNESDAY, JULY 26, 2:15pm - 03:15pm | Booth: 2228 Pavilion Panel, ESL: Software Engineers Are from Pluto and Hardware Engineers Are from Mercury: Can ESL Bridge the Gap?
http://www2.dac.com/data2/43rd/43acceptedpapers.nsf/0/5209DD915A1F07C28725714100656A36?opendocument
THURSDAY, JULY 27, 2:00pm - 4:00pm | Room: 306-308 Session, High-Performance Simulation of Transaction Level and Dataflow Models
http://www2.dac.com/data2/43rd/43acceptedpapers.nsf/websessions/52
CHECK OUT THE ADDITIONAL MEETINGS AT DAC FOR MORE SYSTEMC ACTIVITIES:
http://www2.dac.com/data2/43rd/43acceptedpapers.nsf/webtutsetc?opennavigator&display=addmeetings
SYSTEMC TECHNOLOGY SYMPOSIUM
Monday, July 24, 2006
11:30am – Registration Opens
12:00 – 1:45pm – Meeting and Panel Discussion
5TH NORTH AMERICAN SYSTEM USERS MEETING (NASCUG)
Monday, July 24, 2005
1:30 pm – Registration
2:00 - 5:00 pm – Meeting
5:00 - 6:00 pm – Beer and Wine Reception
LOCATION
Room 200-210
Moscone Convention Center
San Francisco, CA
REGISTER NOW AS SEATING IS LIMITED!
http://www.nascug.org/5thnascug_registration.htm
SPONSORS
Cadence Design Systems, Inc., Celoxica Ltd., CoWare Inc, ESLX, Forte Design Systems, Inc., Mentor Graphics Corporation, Synopsys, Inc., Doulos Ltd., Jeda Technologies
--------------------------------------------
SYSTEMC SYMPOSIUM HIGHLIGHTS
Detailed agenda is available at http://www.mod-marketing/osci
PANEL: ESL ADOPTION: WINNING STRATEGIES FOR THE ORGANIZATION
Moderated by David Maliniak, EDA editor, Electronic Design
Leading design companies have embraced ESL design and transaction-level modeling (TLM) as the next system-on-chip (SoC) design methodology imperative. With simulation speeds of 1,000x faster than RTL and 10x more productive model development time, ESL and TLM technologies are creating new value by enabling significantly earlier architecture definition and software development for SoC designs, and streamlining hardware implementation and system verification.
But what are the implications for the organization? How are design teams expected to work together to deliver this impact to the bottom line?
Join our panel of experts in this lively discussion on the economic impact of ESL, SystemC, and TLM.
PANELISTS
Terry Doherty, Principal Engineer, Emulex
Ryan Bedwell, System-Level Design Manager, Modem Products Division of the Wireless & Mobile Systems Group, Freescale
Tommi Makelainen, Principal Research Engineer and Program Manager, Computer Architecture Laboratory, Nokia Research Center
Loic Le Toumelin, SOC Methodology Process and Tools, Worldwide Director, Cellular Systems Wireless Division, Texas Instruments
SPECIAL PRESENTATION: EXPLORING SYSTEMC/SYSTEMVERILOG INTERACTION
The IEEE has recently ratified SystemVerilog and SystemC as official IEEE standards respectively known as IEEE Std. 1800™-2005 and IEEE Std. 1666™- 2005. The SystemC and SystemVerilog design and verification languages were developed to deliver exponential increases in design productivity in response to the industry’s perennial challenge – continuing exponential increases in design complexity. These languages are increasingly used in a complementary manner in SOC design. The short overview of these languages and their complementary use will be explored.
PRESENTERS
Johny Srouji, Chair of IEEE SystemVerilog WG
Stuart Swan, Technical Chair of IEEE SystemC WG
REGISTER NOW AS SEATING IS LIMITED!
http://www.thttp://www.nascug.org/5thnascug_registration.htm
--------------------------------------------
NASCUG HIGHLIGHTS
AGENDA: http://www.nascug.org/5th_NASCUG_agenda.html
PRESENTATIONS
Patterns and Issues in SystemC Usage
John Aynsley, Doulos Ltd.
Effective Performance Analysis and Visualization of SystemC Models Adam Donlin, Xilinx Inc.
High-Speed Hardware/Software Co-Verification with CPU Model Generator from Software Code Dai Araki, InterDesign Technologies Inc.
Experience of Migration from eVCs to SystemC Modeling Adesh Sontakke, Texas Instruments
Behavioral SystemC Implementation of an MP3 Decoder Portavales Goldstein, State University of Campinas - UNICAMP
PANEL: EXPLORING THE "FUTURES" OF SYSTEMC Moderated by: Mark McDermott, Adjunct Professor, University of Texas; Vice President, Engineering, Coherent Logix, Inc.
Built upon the cooperative effort of combined vendor technology and user experiences, the IEEE has approved the SystemC language as IEEE Std. 1666. Providing a core for virtually all modeling and verification for system-level design, IEEE 1666 provides the foundation for the next generation of technologies and tools developed around the standard. Help us explore what the future holds for this new standard! As we move to even larger systems, how far can the language go in solving even more complex design challenges?
PANELISTS
Functional Verification: Kota Bhaskar, ElementCXI
Mixed Signal Modeling: Dr. Joanne DeGroat, Associate Professor, Ohio State University
RTOS Modeling: David Black, CTO, ESLX, Inc; Member, OSCI Language Working Group
System Level Design: Mark Burton, Founder, GreenSocs; Chairman, OCP-IP SLD Working Group
DON’T’ MISS THE BEER AND WINE RECEPTION AT 5:00PM!
--------------------------------------------
MORE SYSTEMC AND ESL EVENTS AT DAC!
MONDAY, JULY 24, 9:00am - 5:00 pm | Room: 305 Full Day Tutorial, ESL Design Methodology Using SystemC
http://www2.dac.com/data2/43rd/43AcceptedPapers.nsf/0/144092A4CC618F708725714100710B21
MONDAY, JULY 24, 2:00pm - 5:00 pm | Room: 309 Hands-On Tutorial, Using Virtual System Prototypes to Optimize Architectures for Low Power and Other Key Attributes
http://www2.dac.com/data2/43rd/43acceptedpapers.nsf/0/2745A324433E9B09872571410072BAE8
TUESDAY, JULY 25, 2006, 2:00pm - 4:00pm | Room: 307 Special Session, Bridging the System to RTL Verification Gap
http://www2.dac.com/data2/43rd/43acceptedpapers.nsf/websessions/7
WEDNESDAY, JULY 26, 10:30am - 12:00pm | Room: 306-308 Technical Panel, Building a Standard ESL Design and Verification Methodology: Is It Just a Dream?
http://www2.dac.com/data2/43rd/43acceptedpapers.nsf/websessions/22
WEDNESDAY, JULY 26, 2:15pm - 03:15pm | Booth: 2228 Pavilion Panel, ESL: Software Engineers Are from Pluto and Hardware Engineers Are from Mercury: Can ESL Bridge the Gap?
http://www2.dac.com/data2/43rd/43acceptedpapers.nsf/0/5209DD915A1F07C28725714100656A36?opendocument
THURSDAY, JULY 27, 2:00pm - 4:00pm | Room: 306-308 Session, High-Performance Simulation of Transaction Level and Dataflow Models
http://www2.dac.com/data2/43rd/43acceptedpapers.nsf/websessions/52
CHECK OUT THE ADDITIONAL MEETINGS AT DAC FOR MORE SYSTEMC ACTIVITIES:
http://www2.dac.com/data2/43rd/43acceptedpapers.nsf/webtutsetc?opennavigator&display=addmeetings
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